/**
 * *****************************************************************
 * @file    pmu_ctype_map.h
 * @author  WuHao(hwu@andartechs.com.cn)
 * @version 1.0.0
 * @date    2020-11-24
 * @brief   pmu configuration registers address definition
 *
 *                 Copyright (c) 2020, Andar Technologies Inc.
 *                           www.andartechs.com 
 *
 * *****************************************************************
 */
#ifndef __PMU_MAP_H
#define __PMU_MAP_H
#include "adt3102_type_define.h"

//#define pmu_int_state_reg 0x00
#define pmu_int_state_reg_rtc_posedge_bit (1<<4)
#define pmu_int_state_reg_io_posedge_bit (1<<3)
#define pmu_int_state_reg_int_state_shift 0
#define pmu_int_state_reg_int_state_mask ((1<<3)-1)

//#define pmu_int_en_reg 0x01
#define pmu_int_en_reg_ctrl_debug_wakeup_en_bit (1<<2)
#define pmu_int_en_reg_ctrl_rtc_wakeup_en_bit (1<<1)
#define pmu_int_en_reg_ctrl_io_wakeup_en_bit (1<<0)

//#define pmu_int_clear_reg 0x02
#define pmu_int_clear_reg_rtc_posedge_clr_bit (1<<4)
#define pmu_int_clear_reg_io_posedge_clr_bit (1<<3)
#define pmu_int_clear_reg_dbg_wakeup_clr_bit (1<<2)
#define pmu_int_clear_reg_rtc_wakeup_clr_bit (1<<1)
#define pmu_int_clear_reg_io_wakeup_clr_bit (1<<0)

//#define pmu_clk_high_reg 0x03
#define pmu_clk_high_reg_ctrl_swap_clk32k_bit (1<<21)
#define pmu_clk_high_reg_ctrl_adc_dckin_div2_bit (1<<20)
#define pmu_clk_high_reg_ctrl_gpadc_clk_sel_shift 16
#define pmu_clk_high_reg_ctrl_gpadc_clk_sel_mask ((1<<4)-1)
#define pmu_clk_high_reg_ctrl_dsp_clk_sel_bit (1<<15)
#define pmu_clk_high_reg_ctrl_ifadc_inv_sel_bit (1<<14)
#define pmu_clk_high_reg_ctrl_cali_clk_sel_shift 12
#define pmu_clk_high_reg_ctrl_cali_clk_sel_mask ((1<<2)-1)
#define pmu_clk_high_reg_ctrl_apb_clk_sel_shift 8
#define pmu_clk_high_reg_ctrl_apb_clk_sel_mask ((1<<4)-1)
#define pmu_clk_high_reg_ctrl_ahb_clk_sel_shift 4
#define pmu_clk_high_reg_ctrl_ahb_clk_sel_mask ((1<<4)-1)
#define pmu_clk_high_reg_ctrl_32k_clk_sel_shift 2
#define pmu_clk_high_reg_ctrl_32k_clk_sel_mask ((1<<2)-1)
#define pmu_clk_high_reg_ctrl_high_clk_sel_shift 0
#define pmu_clk_high_reg_ctrl_high_clk_sel_mask ((1<<2)-1)

//#define pmu_clk_gate_reg 0x04
#define pmu_clk_gate_reg_pll_test_clk_dsm_en_bit (1<<13)
#define pmu_clk_gate_reg_pll_test_clk_fmcw_en_bit (1<<12)
#define pmu_clk_gate_reg_ctrl_clk_adc_test_en_bit (1<<11)
#define pmu_clk_gate_reg_ctrl_clk_adc_test_12b_en_bit (1<<10)
#define pmu_clk_gate_reg_ctrl_clk_dsamp_en_bit (1<<9)
#define pmu_clk_gate_reg_ctrl_clk_fft_en_bit (1<<8)
#define pmu_clk_gate_reg_ctrl_clk_fir_en_bit (1<<7)
#define pmu_clk_gate_reg_ctrl_clk_ifadc_en_bit (1<<6)
#define pmu_clk_gate_reg_ctrl_clk_cali_en_bit (1<<5)
#define pmu_clk_gate_reg_ctrl_clk_trng_en_bit (1<<4)
#define pmu_clk_gate_reg_ctrl_clk_ssp1_en_bit (1<<3)
#define pmu_clk_gate_reg_ctrl_clk_ssp0_en_bit (1<<2)
#define pmu_clk_gate_reg_ctrl_clk_i2c0_en_bit (1<<1)
#define pmu_clk_gate_reg_ctrl_clk_i2c1_en_bit (1<<0)

//#define pmu_soft_reset_reg 0x05
#define pmu_soft_reset_reg_ctrl_rst_lock_det_n_bit (1<<10)
#define pmu_soft_reset_reg_ctrl_rst_dsamp_n_bit (1<<9)
#define pmu_soft_reset_reg_ctrl_rst_fft_n_bit (1<<8)
#define pmu_soft_reset_reg_ctrl_rst_fir_n_bit (1<<7)
#define pmu_soft_reset_reg_ctrl_rst_ifadc_n_bit (1<<6)
#define pmu_soft_reset_reg_ctrl_rst_cali_n_bit (1<<5)
#define pmu_soft_reset_reg_ctrl_rst_trng_n_bit (1<<4)
#define pmu_soft_reset_reg_ctrl_rst_ssp1_n_bit (1<<3)
#define pmu_soft_reset_reg_ctrl_rst_ssp0_n_bit (1<<2)
#define pmu_soft_reset_reg_ctrl_rst_i2c0_n_bit (1<<1)
#define pmu_soft_reset_reg_ctrl_rst_i2c1_n_bit (1<<0)

//#define pmu_rc32k_calibration_reg 0x06
#define pmu_rc32k_calibration_reg_ctrl_rc32k_cali_alpha_shift 0
#define pmu_rc32k_calibration_reg_ctrl_rc32k_cali_alpha_mask ((1<<4)-1)

//#define pmu_pmu_ctrl_reg 0x07
#define pmu_pmu_ctrl_reg_rc32k_cali_en_bit (1<<10)
#define pmu_pmu_ctrl_reg_ctrl_ldo18bb2_on_bit (1<<9)
#define pmu_pmu_ctrl_reg_ctrl_ldo18bb1_on_bit (1<<8)
#define pmu_pmu_ctrl_reg_ctrl_ldo12_pd_bit (1<<7)
#define pmu_pmu_ctrl_reg_ctrl_bg_33v_pd_bit (1<<6)
#define pmu_pmu_ctrl_reg_ctrl_bg_18v_pd_bit (1<<5)
#define pmu_pmu_ctrl_reg_manu_ctrl_en_bit (1<<4)
#define pmu_pmu_ctrl_reg_ctrl_hold_ana_cfg_bit (1<<3)
#define pmu_pmu_ctrl_reg_ctrl_iso_n_bit (1<<2)
#define pmu_pmu_ctrl_reg_ctrl_ram_iso_n_bit (1<<1)
#define pmu_pmu_ctrl_reg_ctrl_ram_on_bit (1<<0)

//#define pmu_pmu_state 0x08
#define pmu_pmu_state_cur_state_shift 16
#define pmu_pmu_state_cur_state_mask ((1<<3)-1)
#define pmu_pmu_state_32k_prd_shift 0
#define pmu_pmu_state_32k_prd_mask ((1<<16)-1)

//#define pmu_pmu_stage_time 0x09
#define pmu_pmu_stage_time_powering_down_time_shift 16
#define pmu_pmu_stage_time_powering_down_time_mask ((1<<16)-1)
#define pmu_pmu_stage_time_powering_up_time_shift 0
#define pmu_pmu_stage_time_powering_up_time_mask ((1<<16)-1)

//#define pmu_reg_ext_clk_en_reg 0x0a
#define pmu_reg_ext_clk_en_reg_rom_ext_en_bit (1<<13)
#define pmu_reg_ext_clk_en_reg_iram_ext_en_bit (1<<12)
#define pmu_reg_ext_clk_en_reg_sram_ext_en_bit (1<<11)
#define pmu_reg_ext_clk_en_reg_fir_fifo_ext_en_bit (1<<10)
#define pmu_reg_ext_clk_en_reg_cnr_high_ext_en_bit (1<<9)
#define pmu_reg_ext_clk_en_reg_fmcw_dsm_ext_en_bit (1<<8)
#define pmu_reg_ext_clk_en_reg_dsp_ahb_ext_en_bit (1<<7)
#define pmu_reg_ext_clk_en_reg_rfc_apb_ext_en_bit (1<<6)
#define pmu_reg_ext_clk_en_reg_dma_ahb_ext_en_bit (1<<5)
#define pmu_reg_ext_clk_en_reg_gpio_ahb_ext_en_bit (1<<4)
#define pmu_reg_ext_clk_en_reg_i2c0_apb_ext_en_bit (1<<3)
#define pmu_reg_ext_clk_en_reg_i2c1_apb_ext_en_bit (1<<2)
#define pmu_reg_ext_clk_en_reg_mcu_ahb_ext_en_bit (1<<1)
#define pmu_reg_ext_clk_en_reg_pmu_apb_ext_en_bit (1<<0)

//#define pmu_mcu_stcalib 0x0b

//#define pmu_sram_cfg 0x0c
#define pmu_sram_cfg_sram_retn_sel_bit (1<<9)
#define pmu_sram_cfg_sram_emab_shift 6
#define pmu_sram_cfg_sram_emab_mask ((1<<3)-1)
#define pmu_sram_cfg_sram_emaa_shift 3
#define pmu_sram_cfg_sram_emaa_mask ((1<<3)-1)
#define pmu_sram_cfg_sram_ema_shift 0
#define pmu_sram_cfg_sram_ema_mask ((1<<3)-1)

//#define pmu_clk_src_cfg 0x0d
#define pmu_clk_src_cfg_rc32k_clk_en_bit (1<<3)
#define pmu_clk_src_cfg_rc32k_en_bit (1<<2)
#define pmu_clk_src_cfg_xo32k_bypass_bit (1<<1)
#define pmu_clk_src_cfg_xo32k_en_bit (1<<0)

//#define pmu_rst_src_flag 0x0e
#define pmu_rst_src_flag_sys_bit (1<<2)
#define pmu_rst_src_flag_wdt_bit (1<<1)
#define pmu_rst_src_flag_pad_por_bit (1<<0)

//#define pmu_rst_src_clear 0x0f
#define pmu_rst_src_clear_sys_clr_bit (1<<2)
#define pmu_rst_src_clear_wdt_clr_bit (1<<1)
#define pmu_rst_src_clear_pad_por_clr_bit (1<<0)

//#define pmu_slp_xo50m_cfg 0x10
#define pmu_slp_xo50m_cfg_slp_xo50m_reg2_shift 4
#define pmu_slp_xo50m_cfg_slp_xo50m_reg2_mask ((1<<8)-1)
#define pmu_slp_xo50m_cfg_slp_xo50m_reg1_shift 0
#define pmu_slp_xo50m_cfg_slp_xo50m_reg1_mask ((1<<4)-1)

//#define pmu_slp_plli_ctrl_reg 0x11
#define pmu_slp_plli_ctrl_reg_slp_plli_en_ldovco_bit (1<<12)
#define pmu_slp_plli_ctrl_reg_slp_plli_en_ldopll_bit (1<<11)
#define pmu_slp_plli_ctrl_reg_slp_plli_en_bias_bit (1<<10)
#define pmu_slp_plli_ctrl_reg_slp_plli_en_pll_bit (1<<9)
#define pmu_slp_plli_ctrl_reg_slp_plli_en_ckdig_125m_bit (1<<8)
#define pmu_slp_plli_ctrl_reg_slp_xo50m_en_bit (1<<7)
#define pmu_slp_plli_ctrl_reg_slp_xo50m_mode_bit (1<<6)
#define pmu_slp_plli_ctrl_reg_slp_xo50m_en_ckdig_bit (1<<5)
#define pmu_slp_plli_ctrl_reg_slp_xo50m_en_ckpll_bit (1<<4)
#define pmu_slp_plli_ctrl_reg_slp_xo50m_en_refclk_out_bit (1<<3)
#define pmu_slp_plli_ctrl_reg_slp_xo50m_en_ckbist_bit (1<<2)
#define pmu_slp_plli_ctrl_reg_slp_plli_en_ckplln_bit (1<<1)
#define pmu_slp_plli_ctrl_reg_slp_plli_en_ckadc_bit (1<<0)

//#define pmu_slp_ldo_bg_reg_reg 0x12
#define pmu_slp_ldo_bg_reg_reg_slp_ldo_bg_reg_shift 0
#define pmu_slp_ldo_bg_reg_reg_slp_ldo_bg_reg_mask ((1<<16)-1)

//#define pmu_slp_power_ctrl_reg 0x13
#define pmu_slp_power_ctrl_reg_slp_ram_iso_n_bit (1<<4)
#define pmu_slp_power_ctrl_reg_slp_ram_on_bit (1<<3)
#define pmu_slp_power_ctrl_reg_slp_ldo12_pd_bit (1<<2)
#define pmu_slp_power_ctrl_reg_slp_bg_33v_pd_bit (1<<1)
#define pmu_slp_power_ctrl_reg_slp_bg_18v_pd_bit (1<<0)

//#define pmu_slp_ldo12n_rega_reg 0x14
#define pmu_slp_ldo12n_rega_reg_slp_ldo12_lp_vcfg_shift 10
#define pmu_slp_ldo12n_rega_reg_slp_ldo12_lp_vcfg_mask ((1<<3)-1)
#define pmu_slp_ldo12n_rega_reg_slp_ldo12_hp_vcfg_shift 8
#define pmu_slp_ldo12n_rega_reg_slp_ldo12_hp_vcfg_mask ((1<<2)-1)
#define pmu_slp_ldo12n_rega_reg_slp_ldo12_reg_shift 0
#define pmu_slp_ldo12n_rega_reg_slp_ldo12_reg_mask ((1<<8)-1)

//#define pmu_plli_lock_ctrl 0x15
#define pmu_plli_lock_ctrl_sel_clk_ref_bit (1<<2)
#define pmu_plli_lock_ctrl_cnt_clear_bit (1<<1)
#define pmu_plli_lock_ctrl_cnt_enable_bit (1<<0)

//#define pmu_plli_lock_result 0x16

typedef struct
{
  __IO uint32 pmu_int_state_reg ;
  __IO uint32 pmu_int_en_reg ;
  __IO uint32 pmu_int_clear_reg ;
  __IO uint32 pmu_clk_high_reg ;
  __IO uint32 pmu_clk_gate_reg ;
  __IO uint32 pmu_soft_reset_reg ;
  __IO uint32 pmu_rc32k_calibration_reg ;
  __IO uint32 pmu_pmu_ctrl_reg ;
  __IO uint32 pmu_pmu_state ;
  __IO uint32 pmu_pmu_stage_time ;
  __IO uint32 pmu_reg_ext_clk_en_reg ;
  __IO uint32 pmu_mcu_stcalib ;
  __IO uint32 pmu_sram_cfg ;
  __IO uint32 pmu_clk_src_cfg ;
  __IO uint32 pmu_rst_src_flag ;
  __IO uint32 pmu_rst_src_clear ;
  __IO uint32 pmu_slp_xo50m_cfg ;
  __IO uint32 pmu_slp_plli_ctrl_reg ;
  __IO uint32 pmu_slp_ldo_bg_reg_reg ;
  __IO uint32 pmu_slp_power_ctrl_reg ;
  __IO uint32 pmu_slp_ldo12n_rega_reg ;
  __IO uint32 pmu_plli_lock_ctrl ;
  __IO uint32 pmu_plli_lock_result ;
}PMU_TypeDef;

#endif
